Reference circuits are frequently found in integrated circuit devices. A reference circuit provides a voltage or current level of known value. This voltage or current reference may be duplicated, or mirrored, for use across the integrated circuit. References are used to establish on-chip power supply levels, signal thresholds, and to insure stable operation of analog amplifiers, among other known applications.
Reference circuits can be categorized as non-biased or self-biased. In a non-biased circuit, the reference is generated by simply conducting current through a device or series of devices. For example, current may be conducted through a series of resistors in a voltage divider. Alternatively, current may be conducted through a diode or series of diodes. A diode drop, or summation of diode drops, is used as a reference voltage. These non-biased reference circuits are simple to construct and typically yield predictable results. However, non-biased references may suffer from several disadvantages. For example, resistor dividers are directly dependent on variations in supply voltages. Further, the current draw for the reference circuit can be large unless very high value resistors are used, and such resistors typically require large circuit areas to construct. Diode series are more predictable than resistor dividers but current draw is still an issue. Hence is can be difficult to construct non-biased reference circuits with low power consumption.
Self-biased circuits use transistor biasing, rather than voltage division, to establish the reference current. Ideally, a self-biased circuit is designed such that the voltage or current reference depends solely on device parameters and layout ratios while cancelling out dependence on the supply voltage. The resulting reference current or voltage is said to have higher output impedance since it is less susceptible to changes in the supply voltage. In addition, a self-biasing circuit is designed to operate with low power consumption. Generally, self-biased reference circuits are more suited to low power applications.
A well-known self-biased reference circuit is the beta-multiplier. In the beta-multiplier, a PMOS mirror circuit and a NMOS mirror circuit are arranged such that each mirror circuit replicates the current from the other circuit. Further, one of the mirrors includes a mismatched output transistor—one have a larger width than the input transistor—coupled to an output source resistor. The operating point of the circuit is mathematically determined by the beta (β) of the transistors, the width ratio of the mismatched transistors, and the size of the resistor. The beta-multiplier circuit thereby generates a current reference substantially independent of the voltage supply and with relatively low power consumption.
A significant issued with self-biased reference circuits in general, and beta-multiplier circuits in particular, is that they have two stable DC operating states. One state is an active state where both of the current mirrors conduct current and the desired current reference is generated. The other state is an inactive state where both current mirrors are OFF and no current reference is generated. To avoid the inactive state, it is common in the art to use a dedicated start-up circuit to force the self-biased reference circuit into the active state during integrated circuit power-up. After a start-up operation is completed, the start-up circuit is shut off. The active state, self-biased reference circuit is then allowed to settle to its stable operating point.
U.S. Pat. No. 7,755,419 to Rao, el al, discloses an implementation of a beta-multiplier reference circuit with a start-up circuit. Referring now to FIG. 5, a circuit schematic block diagram illustrates this prior art, self-biased reference circuit 400. The circuit 400 includes a reference circuit 404 and a start-up circuit 408. The circuit 400 is powered from a high voltage supply VCC 412 and a low voltage supply VSS 414. The beta-multiplier reference circuit 404 includes (1) a PMOS current mirror of transistors P21 416 and P22 420, (2) a NMOS current mirror of transistors N21 424 and N22 428, (3) a resistor R21 432, and (4) an output section of transistor P23 436 and resistor R22 440. The output transistor N22 428 of the NMOS mirror has a width K times larger than the input transistor N21 424. Neglecting mismatch and λ effects, if the reference circuit 404 is operating in the active state, then the PMOS and NMOS mirrors force currents I1 and I2 to match. As a result, the gate-to-source voltages of the NMOS mirror transistors are governed by the equation VGSN21=VGSN22+IR. Substituting transistor operating formulas for the gate-to-source voltages, it is found that the reference current I2 is proportional to an equation based on (1) the value of the resistor R, (2) the value of beta for transistor N21, and (2) the value of K. Therefore, the reference current I2 value is not directly dependent on the power supply VCC 412.
The prior art start-up circuit 408 includes (1) a current reference transistor N23 460, (2) a current supply transistor P24 464, and (3) a switching transistor P25 456. When the integrated circuit is powered OFF, VCC 412 and VSS 414 are at the same level. When the integrated circuit is first powered ON, VCC 412 immediately rises to a high level with respect to VSS 414. At that moment, the capacitance of transistor N23 460 will cause the initial voltage Start 468 to stay at a low level. Therefore, the gate of transistor P25 456 is pulled toward VSS 414, and the transistor is turned ON. Transistor P25 456 will conduct current to pull voltage VBN 448 towards VCC 412. This will cause current I1 to flow through transistor N21 424 and elevated voltage VBN 448 such that mirror input transistor N21 424 and output transistor N22 428 are ON. Output current I2 will flow through N22 428 to induce gate voltage VBP 452 onto PMOS mirror input transistor P22 420 and output transistor P21 416. This will cause current I1 to flow. At this point all of the transistors in the beta-multiplier circuit are ON, and the circuit is in the active state. Voltage VBP 452 will bias output transistor P23 436 and induce current I3 through output resistor R22 440 to generate the voltage reference VREF 444. The start-up circuit 408 is designed such that the transistor P24 464 will dominate a voltage divider created by transistors P24 464 and N23 460. As a result, the voltage Start 468 rapidly rises toward VCC 412 until transistor P25 456 is shut OFF. Once P25 shuts OFF, the beta-multiplier circuit 404 will settle to the active state operating point as described above.
There are two practical problems with this prior art implementation. First, the current conducted through the self-biased reference circuit 404 during start-up will substantially exceed the nominal, or steady-state, level to cause much higher power consumption. This higher current is due to a large bias voltage VBN 448 forced onto the NMOS mirror input transistor N21 424 during start-up. Further, the large start-up inrush current I1 is replicated in current I2 and output current I3, as well as any other branches referenced to the voltage VBP 452. These large currents are not compatible with low-power operation and can be a serious problem for switched capacitor (SC) filters, dynamic bias circuits, and other sensitive analog circuits. A second problem is that, even during steady, active state operation, the output current I2 of the beta-multiplier circuit 404 has a strong supply voltage dependence (low output impedance). The simple, single-stage PMOS and NMOS current mirrors are influenced by variation in the supply voltage VCC 412 to cause modulation of the currents I1 and I2 (and all subsequent reproductions). Therefore, the current and voltage references from the prior art circuit are not optimal.
Referring now to FIG. 6, a circuit schematic block diagram illustrates a prior art, self-biased reference circuit 500 that attempts to address these two issues. A beta-multiplier circuit 504 is formed with cascode-type current mirrors 516 and 518. These cascode current mirrors 516 and 518 have higher output impedance than the simple current mirrors of the prior art circuit in FIG. 5. Referring again to FIG. 6, the NMOS cascode current mirror 516 includes transistors N1 520, NC1 524, N2 528, and NC2 532. The NMOS transistors form two stacked mirrors. Each mirror is self-biasing from the input current I1, has high output impedance and low offset error. The NMOS cascode mirror 516 requires a minimum input voltage of two diode drops and exhibits an output compliance voltage of about one diode drop plus a saturation voltage. The resistor R0 534 in the source path of N2 528 overlays the beta-multiplier function onto the output current I2. The PMOS cascode current mirror 518 includes transistors P1 544, PC1 548, P2 552, and PC2 556. The PMOS transistors are configured as a low-voltage, cascode current mirror. In this configuration, the minimum required input voltage drop for the mirror is only a single diode drop while the output compliance voltage is two saturation voltages. To achieve low minimum input voltage operation, the PMOS cascode current mirror 518 requires an additional cascode bias voltage VPC 568. This cascode bias voltage VPC 568 is generated by diode-connected transistor PC3 560. Transistors N3 574, N4 576, P4 570, and PC4 572 allow the PMOS bias voltages VP 564 and VPC 568 to mirror the reference current Iref to the bias voltage generating transistor PC3 560. Transistors P5 580 and PC5 582 and resistor R1 584 are used to generate reference voltage VREF 586.
The prior start-up circuit 508 includes (1) switch transistor NST 588, (2) current source transistor N5 590, and (3) capacitor CST 592. Immediately after powering up the integrated circuit, the voltage START 594 will be about the same as the supply voltage VCC 512 due to the presence of the capacitor CST 592. As a result, the switch transistor NST 588 will be biased to the ON state. Transistor NST 588 will therefore connect together the nodes VPC 568 and VNC 540 which will cause current to flow in the NMOS and PMOS current mirrors 516 and 518. The reference current IREF will bias diode-connected transistor N4 576 to generate a bias voltage 578 that is further connected to current source transistor N5 590. Current source transistor N5 590 discharges the capacitor CST 592 such that the START voltage 594 is eventually pulled to below the turn-on voltage for NST 588. At this point, the start-up circuit 508 is disabled, and the bias-multiplier circuit 504 is allowed to settle to steady state.
It is found that minimum operating supply voltage, or headroom voltage, for the prior art beta-multiplier circuit 504 is governed by the left branch of each current mirror 516 and 518, composed of the diode-connected, NMOS transistors N1 520 and NC1 524 and the PMOS transistors P1 544 and PC1 548. The transistors N1 520 and NC1 524 are typically biased in the sub-threshold region since this operating mode reduces the effect of the R0 tolerance. In this operating mode, the minimum voltage headroom necessary to operate the beta-multiplier circuit 504 is found to be about two NMOS transistor diode drops plus two PMOS transistor saturation voltages, or about VCCmin=2VTN+2VDSATP.
It is further found that the prior art start-up circuit 508 requires a minimum supply voltage of about two NMOS transistor diode drops plus one NMOS transistor drain-to-source voltage and one PMOS transistor gate-to-source voltage, or about VCCmin=2VTN+2VDSN+VGSP. This minimum supply voltage includes the voltage across the NMOS diode-connected transistors N1 520 and NC1 524, the drain-to-source drop of the switch transistor NST 588, and the gate-to-source drop of the voltage bias transistor PC3 560. In addition, the voltage necessary to turn ON the start-up switch transistor NST 588 is found to be in excess of VSTART=2 VTN+VGSNST. This analysis reveals the main disadvantage of the prior art start-up circuit 508. Namely, the minimum supply voltage VCCmin necessary for the correct operation of the start-up circuit 508 is found to be higher than the minimum supply voltage VCCmin required to operate the beta-multiplier current 504. To optimize the combined reference circuit 500, it is essential that the start-up minimum supply voltage be reduced.